All aspects of modelling, operation, and control of power and energy systems. On-line fault detection and isolation; fault decision theory; diagnosis, monitoring and supervision based on hardware and analytical redundancy. Modeling, supervision, control, and diagnosis of automotive systems, power trains, vehicle dynamic systems, automotive sensors, integrated traffic, and in-vehicle communication. Theory and application of control engineering and artificial intelligence techniques to the maritime field.
Navigation, guidance and control, monitoring and surveillance, fault diagnosis, optimization, planning, modelling, identification, human factors and control architectures. Dynamics, control, and mission control of all aeronautical and space related vehicles and vehicle systems. Ground transportation systems road and guided transport and air traffic control systems for both passengers and transported goods. Generic system methodologies and technologies applicable to intelligent autonomous vehicles including mobile robots on land, at sea, or in space.
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Modeling, simulation and control aspects of agricultural machines, systems, and processes; Tools, techniques and methodologies for crop production and animal husbandry; post-harvest systems and processes grading, drying, storage of crops ; Food processing methods and systems efficiency, quality and safety ; Environmental and climate control of greenhouses, vertical farming environments, warehouses and animal houses; Energy efficiency and precision agricultural issues.
Applications of systems, modelling, informatics and control concepts, methodology and techniques in biology, physiology, medicine and healthcare. Modelling and control methodologies for reliable management of natural resources and prevention and mitigation of environmental hazards and disasters. Application areas include, but are not limited to, urban and rural water systems and pollution control of soil, water, and air. Promotion of research and development in all major areas of biotechnology where computers are used to aid bioprocess design, supervision, diagnosis, operation, optimisation and control.
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Search Site. Advanced Search…. Using a TLM model and the standard protection provided by the Internet allows both sides to hide the content of their IPs, without compromising any functionality. Both teams can verify their own work using this framework. Table 1 shows examples of the hardware and software components.
We applied our framework to the design of a 3D graphics hardware accelerator that is integrated in a SoC platform.
Using generic 3D graphics application on a workstation, the software team can produce the results they desire without the hardware or a device driver. This allows them to develop the upper layers of the software stack. However, in the lower layers, the device drivers cannot be written and tested without the hardware. Our framework enables the software and hardware teams to adopt a uniform set of test patterns for verifying their designs.
Reproducibility is a key aspect of our framework. It allows for instant feedback on the latest committed design, be it hardware or software, from other members of the team. Yet, the use of TLM means that access to the inner details of each component can be controlled, monitored, and managed. For example, if the hardware team do not wish to reveal an IP to the other members, they can do so by exposing only its interfaces, so that users can still use the component for their own subsystems.
The use of the Internet does carry some risks, but there are already a large set of established protocols and mechanisms, such as the secure sockets layer SSL or virtual private network VPN , that can minimize any risks caused. From a software perspective, a full system consists of applications, the operating systems, device drivers, API, etc.
In our 3D case study of hardware-software design flow, the software development environment is shown in Figure 5 , and the factors of the corresponding components is shown in Table 2. We explain further the components in the sections below. A strategic design choice we made from the start of the project was to use open source resources and industry standards.
ARM processors are a common processor to embedded systems. The software designers build the guest ARM software environment under host Intel x86 processor. Finally, they execute the software under guest platform QEMU. According to the 3D graphics test benches shown in Figure 6 , The software designers implemented four functions in the device driver. By calling the mmap function, the 3D graphics test benches can move 3D vertices into the 3D vertex buffer.
The RE stores its results in the bit temporary frame buffer, and then raises an IRQ to notify the ISR of 3D graphics device driver to truncate the pixel data from to bits.
The truncation is necessitated by the difference in bit width between the development platform and the 3D graphics SoC. Finally, the 3D graphics object is displayed on the output screen. The software designers development two types of 3D graphics test benches. The first type of test benches accesses 3D graphics device driver directly and owns only one object per frame. We have four 3D graphics test benches as shown in Table 3. The first two rows show the images in the test benches, and the last row gives the complexity of these test benches. Each vertex consists of 10 words.
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Each test bench has four modes, namely, the GE mode, RE mode, single frame mode, and multi-frame mode. The latter implements the 3D graphics SoC hardware. After considering all the necessary operations, we defined two directions of communication consisting of seven types of operations, as shown in Figure 7.
The QEMU interface has three threads that allow it to handle different tasks. This thread will issue mReadRequest and mWriteRequest requests through an outgoing socket, and receives mReadAck acknowledgment through an incoming socket. The QEMU receiver acts as a slave interface and an interrupt controller. The framebuffer viewer is used to output the file, as shown in Figure 8. The diff command can also be used to compare the data to the expected log data [ 28 ].
This section introduces the hardware development environment of the proposed co-design framework consisting of two hardware parts. Figure 9 presents the block diagram of the full development environment. In principle, the software and hardware teams work concurrently, but in physical locations that are geographically dispersed. Therefore, the Internet is the best media for maintaining continuous communication between the teams. The second part is the 3D graphics SoC itself.
This main part of the hardware design is implemented in SystemC using different abstraction levels. The block diagram is shown on the left-hand side of Figure 9. The SCI contains a master and a slave ports, as well as six main processes as shown on the right-hand side of Figure 7. The master read, master write, slave read , and slave write processes communicate with system bus.
The SC receiver process gathers all incoming messages from the QEMU, and forwards them to the corresponding processes. These can be reproduced later without full software execution. The SCTracer also stores the frame buffer in a file for checking.
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This will aid in offine debugging and architectural design space exploration. To complete an mWrite operation, the SCI will notify the SC receiver that it has consumed the packet, and so the SC receiver may go ahead and receive another packet. However, the state of read data needs to wait for the QEMU to send a read acknowledgement response. Figure 12 presents the static structure of the SCI, and then Figures 10 and 11 describe the dynamic state transition of the SCI according to the interaction of system operation.
However, these figures are unable to detect certain problems, such as deadlocks. Some processes will hold resources, while at the same time requiring other resources held by others.
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The result is a deadlock. Figure 13 shows two types of deadlock that can happen in the SCI. According to our 3D graphics test benches, the master read process usually requires the values of the registers in the 3D graphics SoC. However, this happens less frequently than the slave read process needs to read data from the 3D graphics SoC. Therefore, to resolve this deadlock, we force the master read process to give up the SC receiver.
The QEMU will be suspended until this happens. The second type of deadlock is shown at the bottom of Figure During the time when the application is writing to the control registers, the 3D graphics SoC may concurrently attempt to read data from the memory of the QEMU. A deadlock occurs as the master write process is unable to lock the bus, but the slave read is unable to complete its data request via the SC receiver.
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